An ADC is a device, which converts an analog input signal into digital output data. The ADC samples the analog input signal and converts the sampled analog input signal into digital data. Among ADCs, a SAR ADC approximates the sampled input by sequentially increasing or decreasing its internal generated reference, starting with the most significant bit. A typical SAR ADC includes an N-bit (where N is an integer equal to or greater than 1) Digital-to-Analog Converter (DAC), a sample and hold, a comparator and a SAR logic core. The N-bit DAC converts an N-bit digital data into a corresponding reference voltage. The comparator compares the analog voltage generated from the N-bit DAC with the sampled analog input signal. If the analog input signal is greater than the reference voltage, the comparator generates a high-level signal, e.g. a signal having a logic value of 1. If the analog voltage is greater than the analog input signal, the comparator generates a low-level signal, e.g. a signal having a logic value of 0.
When setting the Most Significant Bit (MSB) of the digital data input of the N-bit DAC to a logic value of 1, and comparing the analog input signal with the reference voltage generated from the N-bit DAC, the MSB of the N-bit digital data can be determined. Next, the above-described comparison process is repeated for the remaining bits by sequentially changing a subsequent bit of the digital data input of the N-bit DAC to determine the N-bit digital data corresponding to the analog input signal.
One of the most common implementations of the SAR ADC, the charge-redistribution SAR ADC, uses a charge scaling DAC. The charge scaling DAC includes a capacitor array of individually switched weighted capacitors. The successive approximation and the DAC is used to perform a, often binary, search by selectively switching an amount of charge upon each capacitor in the array based on a comparator and the successive approximation register.
The search requires charging and/or discharging of one or more capacitors of the capacitor array at each iteration with a charge, which dependents on the state of the capacitors in the array and the decision made by the comparator. Accordingly, a state dependent current is drawn by the capacitor array from the source supplying the reference voltage signal.
This DAC switching causes a charge-redistribution SAR ADC to draw input signal/output data dependent current from the reference voltage source. The output impedance of the reference voltage source has to be adapted to the varying currents drawn by the charge-redistribution SAR ADC since the voltage stability of the reference voltage source is crucial for the accuracy of the charge-redistribution SAR ADC.